Method for forming free standing microstructures

ABSTRACT

A method of forming free standing microstructures includes providing a substrate and forming a sacrificial layer on the substrate. A thin-film structural layer is then formed around and over the sacrificial layer. The sacrificial layer may be formed from an electrically conductive or non-electrically conductive material in certain embodiments of the invention. Nanometer-scale pores are then introduced through the thin-film structural layer by a non-lithographic method, such as anodic etching. Via the pores, at least a portion of the sacrificial layer is etched away or otherwise removed from underneath the thin-film structural layer. The free standing microstructures may be sealed by application of a sealing layer on top thereof. The microstructure may form an encapsulating cavity and provide integrated on-wafer packaging if separate microdevices are disposed inside the cavity. The entire process may be done at or near room temperature in some cases.

REFERENCE TO RELATED APPLICATIONS

This Application claims priority to U.S. Provisional Patent Application No. 60/686,713 filed on Jun. 2, 2005. U.S. Provisional Patent Application No. 60/686,713 is incorporated by reference as if set forth fully herein.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT

The U.S. Government may have a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Grant No. DAAH01-99-C-R220 and W31P4Q-05-P-R012 awarded by DARPA.

FIELD OF THE INVENTION

The field of the invention relates to thin-film microstructures formed by surface micromachining processes in the field of Micro-Electro-Mechanical-Systems (MEMS).

BACKGROUND OF THE INVENTION

Although MEMS-based products are increasingly being used in commercial and research applications, the packaging of the MEMS microdevices is usually developed on a case-by-case basis in-house and remains as a significant obstacle to large scale commercial production. Due to the sensitive and fragile nature of the free standing microstructures formed in many MEMS devices, the packaging process often amounts to a significant portion (e.g., as much as 80-90%) of the cost of a MEMS-based product. The so called “on-wafer packaging” (also known as zero-level or device-level packaging) of MEMS devices on a single wafer, i.e., packaging the delicate devices in a protective housing on the wafer before the wafer is ready for dicing, has long been recognized as a promising approach, because it allows the use of packaging procedures similar to those used for regular electronics manufacturing in producing a large numbers of MEMS-based devices.

In general, the on-wafer packaging (or encapsulation) approaches fall into two categories: (1) wafer bonding packaging and (2) integrated thin-film packaging. In the wafer bonding approach, a separate substrate is bonded to the MEMS wafer to cap the MEMS components using a wide variety of bonding techniques. While wafer bonding has a proven track record and is being widely used in industry, integrated thin-film packaging has long been considered to be a potentially more cost effective approach for mass production.

In the so-called integrated thin-film packaging approach, the packaging process is carried out on the same wafer where the MEMS devices are fabricated by adding extra steps to the surface micromachining process used to construct the device. For example, an additional sacrificial layer is deposited on top of an unreleased microdevice and then covered by a thin-film structural layer that will eventually form a cavity and encapsulate the microdevice inside. The device is released after the sacrificial layer is removed through the etch holes opened in the structural layer (e.g., encapsulating shell). One known approach is to use wet or gas etchants that pass through a limited number of micrometer-sized etch holes that are lithographically opened in the encapsulation shell. The MEMS package is then sealed by conformal deposition of a thin-film on top of the encapsulation layer in an appropriate pressure condition.

Compared with wafer-bonding packaging techniques, integrated thin-film packaging has several advantages including: (1) the use of surface-micromachining batch fabrication processes, thereby avoiding the need for aligning two wafers and the challenges of bonding on “processed” (i.e., not smooth) surfaces; (2) the elimination of the seal ring, allowing much smaller volume cavities, therefore increasing the number of available dice per wafer; and (3) a lower topography. Thin-film encapsulation processes even allow the post-encapsulation processes for additional MEMS or IC steps, if desired.

Despite the anticipated advantages of integrated thin-film packaging, existing encapsulation methods suffer from a few drawbacks for on-wafer packaging. First, because of the lithography and etching techniques employed, the etch holes patterned in the encapsulation shell have a typical size of a few micrometers. Opening vertical etch holes in the encapsulation layer right above the device area is not desirable, because a significant amount of sealing material can diffuse through the etch holes and deposit on the MEMS device surfaces inside the cavity, thereby changing the device characteristics.

While this issue can be alleviated by utilizing laterally directed etch channels, such channels require relatively long times to remove the sacrificial materials out of the cavity, lowering the process throughput and even potentially degrading the mechanical properties of the structure material. Improperly designed lateral etch channels can also lead to excessive gas evacuation time during the sealing process. Consequently, despite more recent advances, the parasitic deposition of sealing material inside the cavity has not been fully prevented.

Polycrystalline silicon (polysilicon) thin-films have been found permeable if made very thin (nanometers) and potentially useful for integrated thin-film encapsulation. However, this thin-film is too thin and weak to serve as an encapsulating structural layer for typical MEMS devices. Thus, this method uses an additional layer of regular thin-film with etch windows, somewhat defeating the purpose of using permeable encapsulation layer.

There thus is a need for a thin-film encapsulation layer that is permeable yet structurally strong enough to freely stand as an encapsulation shell. The need for structural strength means that the use of very thin layers should be avoided. The need for permeability suggests that the pores should be very small so they are sealed quickly before the sealing material passes through them. Yet, the sacrificial material needs to be removed through the tiny pores. The two seemingly conflicting requirements can be met, if the pores are very small but highly populated. Considering all the requirements, it is desired to have a relatively thick (i.e., on the order of micrometers) encapsulation layer with highly populated nanometer-scale pores formed through the layer preferably in a normal orientation.

Moreover, because many MEMS-based devices use metals, which cannot withstand high processing temperatures, there is a need for thin-film encapsulation methods that avoid high-temperature processing steps. Metallic structures (e.g., gold, aluminum) are currently most commonly used in radio-frequency (RF) MEMS devices. These devices, however, cannot be packaged by integrated thin-film packaging if the processing includes high temperature steps.

SUMMARY

In a first embodiment of the invention, a method of forming a free standing microstructure (e.g., a shell or encapsulation structure) includes providing a substrate and forming a sacrificial layer over the substrate. A thin-film structural layer is then formed over and around the sacrificial layer. Nanometer-scale pores are then introduced in the thin-film structural layer. For example, non-lithographic methods may be used to form an array of highly populated, directional pores having diameters in the nanometer range. Via the pores, at least a portion of the sacrificial layer is etched away or otherwise removed from underneath the thin-film structural layer. The thin-film structural layer may be sealed by application of a sealing layer on top thereof.

The free standing structural microstructure or encapsulation layer can be used to enclose one or more microdevices (e.g., MEMS devices). The microdevice may include, for example, an RF-based MEMS device. The process described herein may also be used to liberate or initiate free standing of one or more portions of the MEMS device contained beneath the thin-film structural microstructure or encapsulation layer.

In one aspect of the invention, the sacrificial layer is formed from a ceramic material such as phosphosilicate glass (PSG). In another aspect of the invention, the sacrificial layer may be formed from a polymer material such as, for instance, a photoresist material. In yet another embodiment of the invention, the sacrificial layer may be formed from a metallic material such as aluminum. The thin-film structural layer may be formed using, for example, a ceramic material (e.g., silicon), a metal (e.g., aluminum), or a polymer in combination with an appropriate sacrificial layer of material underlying the same.

In one aspect of the invention, the sacrificial layer is formed at a temperature at or below 300° C. In another aspect of the invention, the sacrificial layer is formed at a temperature that is at or around room temperature. Similarly, in one aspect of the invention, the structural layer may be deposited at or below 300° C. In yet another aspect, the structural layer may be formed at a temperature that is at or around room temperature. Again, similarly, in one aspect of the invention, the sealing layer may be deposited at or below 300° C. In yet another aspect, the sealing layer may be formed at a temperature that is at or around room temperature. In one aspect of the invention, the sacrificial layer, structural layer, and sealing layer are all formed at a temperature at or below 300° C. In yet another aspect, the sacrificial layer, structural layer, and sealing layer are all formed at a temperature that is at or around room temperature.

In one embodiment of the invention, a sacrificial layer is formed on the substrate, and a polymer structural layer is then deposited. The sacrificial layer can be either electrically conductive or non-conductive. Highly populated, highly directional nanopores can be introduced into the polymer layer via ion irradiation followed by etching. The sacrificial layer is then at least partially etched away or otherwise removed. Optionally, the structural layer may be sealed with a sealing layer. The sealing layer may be substantially impermeable to fluids.

In another embodiment of the invention, a sacrificial layer is formed on the substrate, and an aluminum structural layer is then deposited. The sacrificial layer can be either electrically conductive or non-conductive. Highly populated, highly directional nanopores can be introduced into the aluminum layer via anodization etching, which turns the aluminum into alumina at the same time. The sacrificial layer is then at least partially etched away or otherwise removed. If the sacrificial layer is electrically non-conductive, a seed layer is formed on the sacrificial layer before the structural layer and removed before the sacrificial etching. Optionally, the structural layer may be sealed with a sealing layer.

In still another embodiment of the invention, a sacrificial layer is formed on the substrate, and silicon structural layer, such as polysilicon, is then deposited. The sacrificial layer can be either electrically conductive or non-conductive. However, if a non-conductive material, such as a glass layer (e.g., phosphosilicate glass (PSG)) is used for the sacrificial layer, the silicon structural layer should be doped to be conductive. Highly populated, directional nanopores can be introduced into the structural layer via anodization etching. The sacrificial layer is then at least partially etched away or otherwise removed. Optionally, the structural layer may be sealed with a sealing layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D illustrate a fabrication process for forming a porous alumina microstructure.

FIG. 2A schematically illustrates the progression of pore morphology changes in an aluminum thin-film subject to anodization etching.

FIG. 2B illustrates a panel of scanning electron microscope (SEM) cross-sectional images illustrating the progression of pore morphology changes in an aluminum thin-film subject to anodization etching.

FIG. 3 illustrates a SEM cross-sectional image of a porous alumina thin-film microstructure (or encapsulation structure).

FIGS. 4A-4D illustrate a vacuum encapsulation process for the fabrication of a metal Pirani gauge.

FIG. 5 is a graph illustrating the resistance vs. current characteristics of a Pirani gauge sealed in a thin-film encapsulation structure. Calibration data at different pressures is also shown.

FIG. 6 is a graph illustrating the leak rate of two sealed cavities.

FIG. 7A is a top view of an encapsulated coplanar waveguide CPW device as viewed using an optical microscope. The gold (Au) signal line is visible through the transparent porous alumina shell.

FIG. 7B is cross-sectional schematic representation of the encapsulated CPW device taken along the line A-A′ in FIG. 7A.

FIG. 7C is cross-sectional schematic representation of the encapsulated CPW device taken along the line B-B′ in FIG. 7A.

FIG. 8 is a graph illustrating the insertion loss difference between packaged and unpackaged CPW devices.

FIGS. 9A-9D illustrate a fabrication process for forming a free standing porous polysilicon shell.

FIG. 10 is a schematic cross-sectional view of process of subjecting a polysilicon thin-film encapsulating structure to electrochemical etching.

FIG. 11 illustrates a graph showing electrode potential as a function of time during electrochemical etching when a constant current is applied.

FIGS. 12A-12H illustrate a fabrication process for the formation of a Pirani gauge beneath a free standing porous polysilicon shell.

FIGS. 13A-13F illustrate a panel of SEM images of a polysilicon Pirani gauge encapsulated by a porous polysilicon shell that was sealed in vacuum.

FIG. 14 illustrates a graph of the resistance vs. current characteristics of a Pirani gauge in known pressures after the cavity is broken.

FIG. 15 illustrates a graph of the thermal impedance of a Pirani gauge at different pressures. The arrow indicates the thermal impedance of the sealed Pirani gauge.

FIG. 16 illustrates the leak rate of two sealed cavities, inside each of which is a Pirani gauge of different designs.

FIGS. 17A-17B illustrate a process for encapsulating a micro-bridge device in a porous polysilicon shell using a Multi-User MEMS Process (MUMPS) foundry service.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A-1D illustrate a fabrication process for forming a free standing porous alumina microstructure 10. From a thin-film, the microstructure 10 may be formed as a beam, bridge, plate, membrane, or the like. With reference to FIGS. 1A-1D, the fabrication process includes providing a substrate 12. A sacrificial layer 14 is then formed on the substrate 12. The sacrificial layer 14 may be formed from a non-conductive material such as, for example a polymer material such as a photoresist. Alternatively, the sacrificial layer 14 may be formed from a ceramic material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and boron silicate glass (BSG). In still other embodiments (e.g., where aluminum is used for the free standing microstructure), the sacrificial layer 14 may be formed from an electrically conductive material.

A thin-film structural layer 16 is formed over the sacrificial layer 14. Pores are then introduced into the thin-film structural layer 16 through the use of, for example, an anodized etching process. The pores preferably are nanometer-sized pores. In certain embodiments, the structural layer 16 may be formed from a polymer, in which case the pores are introduced by a different method, for example, an ion-irradiation followed by etching. Following pore formation, at least a portion of the sacrificial layer is then etched or otherwise removed from underneath the thin-film structural layer 16.

With respect to anodized porous alumina, the typical pore structure is a hexagonal array of cylindrical-shaped pores with a bottom Al₂O₃ barrier layer. The pore diameter generally ranges from around 10 nm to around 300 nm. To form free standing microstructures, the bottom Al₂O₃ barrier layer needs to be removed to allow the diffusion of etchant(s) through the pores to etch away the sacrificial material.

With reference to FIG. 1A, a thin-film stack was formed on a silicon substrate 12. Going from the bottom to the top in FIG. 1A, the stack consisted of a 0.3 μm thick PECVD oxide layer 18 deposited for insulation purposes, a 1.5 μm thick amorphous silicon (a-Si) sacrificial layer 14, 1000/100 Å thick evaporated titanium/gold (Ti/Au) layers 22, 24, and a 1 μm thick evaporated aluminum (Al) layer 26. FIG. 1B illustrates the aluminum layer 26 undergoing anodized etching. The anodization etching was performed at 40 V constant bias in a 0.3 M oxalic acid solution at room temperature. During the anodization etching process, the current stabilized for a long period, indicating a process of stable pore growth, and then suddenly started to increase steadily accompanied with gas bubble generation. The generation of gas bubbles signified that the etching front had reached the gold (Au) layer 24 and, due to the existence of H₂O in the electrolyte, electrolysis generated O₂ gas. At the same time, the color of the aluminum surface changed from opaque (i.e., the color of aluminum), to translucent and finally to transparent.

The etching process was stopped when the thin film became transparent. The structure of the bottom barrier layer during and after the anodization etching process was completed is shown in the SEM pictures in FIG. 2B (upper, middle, and lower SEM images) and associated schematic representations illustrated in FIG. 2A. As seen in the middle image of FIGS. 2A and 2B, a very thin arched barrier layer (around 10 nm in thickness) with a small void underneath was observed at the bottom of each pore. The arched barrier layer was then removed by a 5 wt % H₃PO₄ wet etching solution for 25 minutes, which also thinned down the pore wall to a diameter of 50 nm. The widening of the pore (or thinning of the pore wall) is best seen in the bottom SEM image shown in FIG. 2B (and illustrated schematically in FIG. 2A).

The 100 Å Au layer 24 was needed to form the numerous thin arches. Without the existence of the Au layer 24, the Ti adhesion layer 22 would have been turned into an oxide layer by the electrolyte with a bottom barrier layer, similar to the typical pore morphology of porous alumina. Next, as best seen in FIG. 1C, the Au layer 24 and Ti layer 22 beneath the porous alumina layer 16 were removed with an Au etchant and a Ti etchant (NH₄OH:H₂O₂:H₂O=1:1:8 on a volume basis) in the area defined by a photoresist mask 28. As seen in FIG. 1D, after the photoresist mask 28 was stripped away, the a-Si sacrificial layer 14 was etched away through the now-formed pores using XeF₂ gas etchant (not shown). The cross-section schematic of free-standing porous alumina structure is displayed in FIG. 1D.

A SEM cross-sectional image of the porous alumina layer 16 is displayed in FIG. 3, where a 1.5 μm thick air gap is visible below the porous alumina layer 16. A magnified view of the cross section of the layer 16 is presented in the insert. The transparent porous alumina layer 16 exhibited a very good quality in terms of mechanical and structural purposes. Porous alumina layers 16 as large as 2 mm a side were successfully obtained without any cracks or wrinkles.

The hermeticity of the encapsulation with the porous alumina thin-film layer 16 was studied by monitoring the pressure change inside the formed package through an encapsulated metal Pirani gauge 30. See FIGS. 4A-4D. The Pirani gauge 30 is a free standing device representing the typical surface-micromachined metal structure(s) that may be positioned inside the encapsulation structures contemplated herein. Moreover, the Pirani gauge 30 can read vacuum level in situ.

Referring now to FIGS. 4A-4D, a schematic illustration of a process for encapsulating a Pirani gauge 30 in an encapsulation package 40 is shown. After the fabrication of a metal Pirani gauge 30, a 4 μm photoresist sacrificial layer 14 was deposited and patterned to define the gap between the Pirani gauge 30 and the alumina thin-film layer 16. The photoresist 14 was hard baked at 120° C. in an oven for 20 minutes to reduce the outgassing during the subsequent processes, followed by an O₂ plasma etching for 2 minutes to roughen the surface for the purpose of improving the adhesion of subsequently deposited metal layers. The thin-film alumina cap 16 above the photoresist sacrificial layer 14 consisted of sputtered 3200 Å Ti adhesion layer 22, evaporated 100 Å Au layer 24, and 15000 Å aluminum layer 16. The anodization etching of the aluminum layer 16 was performed on a 2 cm by 2 cm chip as shown in FIG. 4B. The current compliance was set below 100 mA to reduce the amount of gas bubbles generated at the end of anodization etching process. Next, by using a photoresist mask (not shown), the pores within the thin-film alumina layer 16 over the cavity area were widened by subjecting the sample to a wet etching process using 5 wt % H₃PO₄ etching solution (25 minute exposure). The Ti layer 22 and Au layer 24 (e.g., seed layers) were also removed through the now formed pores. The photoresist mask (not shown), along with the photoresist sacrificial layer 14 below the porous alumina layer 16, was removed by O₂ plasma etching as shown in FIG. 4C. Afterwards, the a-Si sacrificial layer 32 located underneath the Pirani gauge 30 was removed by XeF₂ plasma dry etching.

Vacuum sealing of the package 40 was performed by depositing a sealing layer 34. In a preferred aspect of the invention, the sealing layer 34 is substantially impermeable to fluids (e.g., liquids and gases). In this case, the sealing layer 34 was a PECVD low stress nitride layer of 2.5 μm thickness at 300° C. It should be understood, however, that the entire packaging process may be carried out at or below 300° C. For example, the entire packaging process may be carried out at or around room temperature if a room temperature sacrificial layer 14, 32 and sealing layer 34 are used. As seen in FIG. 4D, the contact pads 36 for electric access to the Pirani gauge 30 were opened.

The package 40 containing the Pirani gauge 30 was then intentionally ruptured to expose the free standing Pirani gauge 30 inside in addition to each layer of the structural layer 16. The Pirani gauge 30 was observed to be free standing in SEM images. See He and Kim, “A Low Temperature Vacuum Package Utilizing Porous Alumina Thin Film Encapsulation,” IEEE Conference on Micro Electro Mechanical Systems held in Istanbul Turkey, January, 2006, which is incorporated by reference as if set forth fully herein.

The pressure inside the sealed package 40 was obtained by matching the resistance-current curve of the sealed Pirani gauge 30 with the resistance-current curves of the Pirani gauge 30 calibrated at different known pressures. FIG. 5 illustrates the resistance-current curves of the Pirani gauge 30. The pressure inside the sealed package 40 was found to be around 8 Torr, a value larger than the deposition pressure of 0.5 Torr. This discrepancy is likely due to the outgassing of the photoresist 14 residue inside the package 40. The hermeticity of the packages 40 was measured from the thermal impedance changes of two sealed Pirani gauges 30. As displayed in FIG. 6, the pressure inside the sealed packages increased slightly (0.4 Torr) over the first 10 days, followed by no noticeable change for the next several days.

Measurements were performed on test packages 40 to measure the extent to which the material of the sealing layer 34 was present inside the structural layer 16. Substantial encroachment of the sealing layer 34 material inside the package 40 would have been likely if lithographically-defined etch holes in the structural shell 16 were to be sealed. The test packages 40 had porous alumina cavities (1.5 μm thick) formed on a bare silicon substrate. After a 5000 Å PECVD oxide deposition layer was formed, the cavity was ruptured using a probe tip and the thickness of oxide on top of the silicon substrate inside the cavity was measured by a NANOSPEC® thin-film measurement system (available from NANOMETRICS, INC., Milpitas, Calif.) using a thin oxide program (low limit: 20 Å). For all the tested packages 40, a “less than 20 Å” result was obtained, indicating the porous alumina shell 16 effectively prevented the internal deposition of the sealing material 34 during the sealing process.

To investigate the RF performance of the porous alumina thin-film package 40, a CPW (Coplanar Waveguide) line (Cr/Au: 250/8000 Å) was packaged on a silicon substrate 12 with high resistivity (>2000 Ω*cm). Following a similar fabrication process as that shown in FIGS. 4A-4D, the porous alumina cavity was formed by removing the Ti/Au layers and the a-Si sacrificial layer sequentially. A PECVD deposition of 1 μm low stress silicon nitride sealed the cavity. The final step was etching away all the films above Au in the electrical contact area.

Cross-sectional and optical microscopic views of the fabricated RF device 50 are shown in FIGS. 7A-7C. The sealed cavity 52 is shown generally in the middle of the microscopic view shown in FIG. 7A, measuring 160 μm by 300 μm, a typical size of a RF switch device. The Au signal lines 54 encapsulated inside the sealed cavity 52 is visible through the transparent structural shell, which is composed of a 1.2 μm thick porous alumina layer 16 and a 1 μm thick silicon nitride sealing film 34.

The insertion loss introduced by the packaging structure was extracted from the difference between the measured insertion loss of a packaged CPW line and an un-packaged CPW line. As seen in FIG. 8, the small difference in insertion loss (less than 0.1 dB up to 40 GHz) demonstrates that the encapsulation structure has a very small influence on the performance of the RF device 50. The small amount of insertion loss that was measured was likely due to the silicon sacrificial layer left in the feed-through area 56 as seen in FIG. 7C. The insertion loss of the RF device 50 may, however, be reduced by removing the sacrificial layer in the feed-through area 56 by adding an additional lithography and etching step.

According to another embodiment of the invention, a free standing microstructure 70 is formed using porous polysilicon. Alternatively, the free standing encapsulation structure 70 may be formed from single crystal silicon. FIGS. 9A-9D illustrate a process for forming such a structure 70. As seen in FIG. 9A, a substrate 72 in the form of a silicon wafer was provided. The substrate 72 was then covered with a low-stress nitride (Si₃N₄) layer 74 having a thickness of 0.6 μm. A sacrificial phosphosilicate glass (PSG) layer 76 having a thickness of 1.5 μm was deposited and patterned on the nitride layer 74. In order to create an electrical contact between the silicon substrate 72 and the later-deposited polysilicon layer for electrochemical etching, openings 78 were made through the silicon nitride layer 74 to the silicon substrate.

In certain embodiments, the thin-film structural layer 16, 70 may be formed from polysilicon or aluminum. In still other embodiments, the thin-film structural layer 16 may be formed using type III-V materials. In particular, the material may include compounds formed with at least one group III element and at least one group V element. These include, by way of example, gallium phosphide (GaP), gallium arsenide (GaAs), indium arsenide (InAs), gallium antimonide (GaSb), and indium antimonide (InSb).

As best seen in FIG. 9B, a 1.5 μm undoped polysilicon layer 80 was then deposited by LPCVD, followed by a 2000 Å PSG deposition layer 82. The polysilicon 80 was symmetrically doped to 0.02 Ω*cm from the PSG layers 82 and 76 by annealing at 1000° C. for about 1 hour in nitrogen. The annealing step also helped release the intrinsic stress in the polysilicon layer 80. Next, all the thin films deposited on the backside of the wafer (not shown) were etched away by reactive ion etching (RIE) to expose the silicon backside surface for electrical contact with the anode in an electrochemical etching device (described below).

After dicing the wafer into 1 cm×1 cm dice, a photoresist mask layer 84 (FIG. 9C) (NR9-8000® negative photoresist) was patterned to define the area for electrochemical etching before each die was mounted in a custom-built TEFLON® cell for electrochemical etching. Details of the electrochemical etching device may be found in the publication entitled “Post-Deposition Porous Etching of Polysilicon: Fabrication and Characterization of Free-Standing Structures,” presented in the ASME International Mechanical Engineering Congress and Exposition in Anaheim, Calif., November 2004, which is incorporated by reference as if set forth fully herein. FIG. 10 schematically illustrates the set up used for electrochemical etching of the polysilicon layer 80. Liquid In—Ga was then painted on the backside of the sample to provide good electrical contact between the sample and the copper jig in the TEFLON® cell. The electrochemical etching was performed in the dark at room temperature in an electrochemical etching solution comprising 49% HF:ethanol in a 1:1 ratio (on a volume basis). FIG. 9C illustrates the formation of the porous polysilicon layer 80 after initiation of electrochemical etching. Once the pores are formed in the polysilicon layer 80, the electrochemical etching solution reaches the interface of the now porous polysilicon layer 80 and the sacrificial phosphosilicate glass (PSG) layer 76. The HF:ethanol etching solution then continues to attack or react with the underlying sacrificial phosphosilicate glass (PSG) layer 76 until the free standing porous polysilicon structure is formed as illustrated in FIG. 9D. In order to alleviate the stiction of the free-standing porous polysilicon layer with the layer 74 when the liquid is evaporated, the device 70 may be dried in supercritical CO₂.

After 200 seconds of electrochemical etching at 4 mA/cm² the porous region in the upper part of the polysilicon layer 80 was visually distinguishable from the solid region underneath. After 250 seconds of electrochemical etching, many trenches were present in the PSG sacrificial layer 76 located right underneath the polysilicon layer 80, signifying that the polysilicon layer 80 was turned porous through its entire thickness and thus HF in the electrochemical solution diffused through the porous polysilicon 80 to attack the PSG layer 76. An irregular etching pattern in the PSG layer 76 was observed. This indicated that pore growth inside the polysilicon layer 80 was not uniform along the thickness direction. It was hypothesized that the electrochemical etching current flows mainly along the polysilicon grain boundaries, resulting in preferential etching and thus a higher pore growth rate at the grain boundaries.

The electrochemical etching current was carefully adjusted to prevent the occurrence of electropolishing in the polysilicon layer 80 under the edge of the photoresist mask 84. In electrochemical etching, when the current density is higher than that of the first peak in the current-potential curve, electropolishing will take place instead of pore formation. However, higher current density and hence higher pore growth rate is preferred in this process in order to prevent the photoresist mask 84 from peeling off in the HF-ethanol electrochemical etching solution and to minimize etching undercut. Generally, a high-enough current density to keep the photoresist mask 84 intact during electrochemical etching but low-enough to prevent the lateral electropolishing was found when the current density was around 4 mA/cm². After 255 seconds of etching, no electropolishing was observed, while the partly etched PSG layer 76 indicated that pores are formed through the entire thickness of the polysilicon 80 in the unmasked area.

Once the free standing encapsulation structure 70 was released, wrinkles and cracks were observed on most of the porous polysilicon structures 80, indicating the presence of high compressive stress in the layer 80. Prior to introduction of the pores, the polysilicon layer 80 was in a low stress condition. It is believed that the compressive stress was introduced in the porous polysilicon layer 80 due to large amount of H₂ generated during the electrochemical etching process. Excessive hydrogen atoms tend to bond to silicon atoms, resulting in a lattice expansion of the Si—Si bond length and thus introducing the compressive stress in porous silicon layer 80. Although the hydrogen can be desorbed from the Si—H bond by annealing at medium temperature (e.g., above 400° C.), a challenge was presented because the porous polysilicon layer 80 starts to free-stand as a membrane or the like soon after the electrochemical etching process is complete, i.e., before annealing can be applied.

In this process, the time window for annealing is thus after the electrochemical etching front reaches the interface of the polysilicon layer 80 and the sacrificial PSG layer 76 and before the HF-based etching solution attacks PSG layer 76 enough to free the polysilicon layer 80 into a free standing structure. It was found that this operating window (i.e., when the pores reached the interface) can be determined by the observation of a sharp increase in electrode potential during the electrochemical etching step.

FIG. 11 illustrates a typical graph of electrode potential versus time for electrochemical etching at a constant current (in this case 4 mA/cm²). The circled portion of FIG. 11 (identified by the arrow) illustrates that the etching front has reached the interface of the porous polysilicon layer 80 and the sacrificial PSG layer 76. As seen in FIG. 11, the electrode potential gradually increases and reaches a relatively constant value. However, when the measured potential (mV) increased sharply, this spike coincided with the moment when the porous etching front reached the interface of the porous polysilicon layer 80 and the sacrificial PSG layer 76.

After the free standing encapsulation structure 70 was taken out of the etching setup and thoroughly cleaned, annealing was then performed using a rapid thermal annealing (RTA) process. In particular, the device 70 was quickly heated at 700° C. for 5 minutes in a nitrogen environment. The effect of the annealing process was noticeable. Porous polysilicon membranes 80 that were not subject to the annealing process were formed with thicknesses of only 100 μm in size. In contrast, porous polysilicon membranes 80 subject to the annealing process were formed with thicknesses as large as 600 μm without any cracks.

Because the HF-based electrochemical etching solution etches the sacrificial PSG layer 76 quickly after diffusing through the porous polysilicon layer 80, the window for annealing is small and accurate determination of this point is needed to stop the etching process. While the process was successful using one die at a time, it may not be as practical for an entire wafer under production conditions. However, a barrier layer (not shown) resistant to the electrolyte (e.g., silicon nitride) may be placed between the polysilicon layer 80 and the PSG layer 76 to solve the problem. The barrier layer can be later removed during the device release process.

With reference to FIGS. 12A-12H, the thin-film encapsulation process was used to seal a micro Pirani gauge 90 that not only measures the vacuum pressure but also represents a free standing polysilicon microstructure. With reference to FIG. 12A, the fabrication process started with a 5000 Å low-stress nitride deposition layer 92 as the insulation layer deposited on a substrate 94, followed by an LPCVD deposition of 1.5 μm a PSG layer 96, which was then patterned as the sacrificial layer between the Pirani bridge gauge 90 and the substrate 94. Next, a 1 μm in situ doped polysilicon layer 98 was deposited by LPCVD and patterned to define the Pirani bridge structure 100 (see FIG. 12H).

With reference to FIG. 12B, a 5 μm PSG sacrificial layer 102 was then formed by two LPCVD depositions. Each deposition was followed by a 1 hour 1000° C. annealing process in the presence of Nitrogen to densify the PSG sacrificial layer 102. The relatively thick PSG sacrificial layer 102 was patterned, and openings 104 were made through the nitride layer 92 to the silicon substrate 94 in order to allow for an electrical path between the polysilicon encapsulation layer (described in more detail below) and silicon substrate 94 for electrochemical etching. With reference to FIG. 12C, a layer of 1.5 μm thick undoped LPCVD polysilicon was then deposited to form an encapsulation layer 106, followed by a 3000 Å LPCVD PSG deposition layer 108. The last polysilicon layer was also symmetrically doped to a resistivity of 0.02 Ω*cm from the PSG layers 102, 108 on both sides by annealing at 1000° C. in nitrogen.

With reference to FIGS. 12C and 12D, the top PSG layer 108 was then stripped off in buffered oxide etchant (BOE), and the insulating layers on the backside were removed by RIE (not shown). After the substrate 94 (e.g., wafer) was diced, each die was processed with a NR9-8000® negative photoresist to define the area of the polysilicon layer 106 into a porous polysilicon encapsulation layer 106. The die was mounted in a TEFLON® cell for the electrochemical etching as describe herein. After stopping the electrochemical etching at the interface of the polysilicon layer 106 and the PSG layer 108 by monitoring the electrode potential as a function of time as described previously the sample was then taken out and cleaned in Piranha solution resulting in the structure illustrated in FIG. 12D. Next, a short RTA annealing (700° C. for 5 minutes) was performed to release the stress generated during the electrochemical etching process.

Then, as illustrated in FIG. 12E, the PSG sacrificial layers 108 were removed by concentrated 49% HF, which obviously diffused through the pores in the 1.5 μm-thick porous polysilicon layer. The release time was approximately one minute regardless of the size of the cavity. On the electrical feedthrough line, the remaining PSG under the polysilicon layer 106 was used to isolate the feedthrough line from the polysilicon shell. The device was designed so that enough PSG is left by time-controlled etching.

The sample was then thoroughly rinsed in DI water and methanol, followed by a supercritical CO₂ drying step. Next, as seen in FIG. 12F, the device 90 was sealed in a vacuum by depositing a sealing layer 110 of polysilicon in LPCVD with a deposition pressure of 179 mTorr and a deposition temperature at 600° C. After sealing, as seen in FIG. 12G, the electrical contact pads 109 were opened outside the cavity by etching away the polysilicon layers 106 and 110 in RIE and the PSG layer 102 in BOE. As seen in FIG. 12H, a 1000 Å gold evaporation layer 112 was formed on the exposed polysilicon feedthrough lines 98 necessary for wire bonding and completed the fabrication process.

FIGS. 13A-13F illustrate SEM pictures of a polysilicon Pirani gauge 90 encapsulated by a porous polysilicon layer 106 or shell. FIG. 13A illustrates an open encapsulation shell 106 that was intentionally clipped to expose the Pirani gauge 90 inside the cavity. FIG. 13B illustrates the serpentine Pirani gauge structure suspended above the substrate by approximately 1 μm and free from the polysilicon shell 106. The encapsulation shell 106, composed of solid polysilicon sealing layer 110 on top of the porous polysilicon layer 106, is shown magnified in FIG. 13C. The porous and solid regions of the polysilicon layers 106, 110, defined by the photoresist mask in the electrochemical etching step, are clearly distinguishable in FIG. 13D. Pore size of the porous polysilicon layer 106 is estimated to be around 5 nm from FIG. 13E. FIG. 13F illustrates an SEM cross-sectional image of the interface between the polysilicon sealing layer 110 and the porous polysilicon layer 106. The transition appears abrupt, which suggests that penetration of the polysilicon sealing layer 110 into the pores is minimal.

The pressure inside the sealed cavity was measured from the encapsulated Pirani gauge 90. The resistance vs. current characteristics of a Pirani gauge 90 was first obtained while vacuum encapsulated. Without affecting the performance of the Pirani gauge 90, the seal on the top empty cavity was then broken intentionally with a probe tip. The entire sample was then placed in a pressure-controlled chamber, where the Pirani gauge 90 was calibrated against known pressures. The pressure inside the sealed cavity, extracted by matching the resistance of the Pirani gauge 90 while sealed with the calibration data obtained above, was around 200 mTorr. FIG. 14 illustrates the resistance vs. current characteristics of the Pirani gauge 90 after the cavity was broken. The extracted pressure of 200 mTorr was consistent with the deposition pressure of the sealing polysilicon thin film (179 mTorr). The residual gas inside the cavity could be H₂ byproduct produced during the polysilicon deposition or from the outgassing of the remaining PSG plug in the feed-through channel.

A better interpretation of the data plotted in FIG. 14 is to transfer the resistance vs. pressure curve into a curve of thermal impedance vs. pressure. It was found that even though the resistance of the Pirani gauge 90 drifts over time, the thermal impedance remains relatively constant at a given ambient pressure. The thermal impedance (T.I.) is defined as ${{T.I.} = \frac{T_{avg}}{P_{E}}},{T_{avg} = {\frac{1}{\xi}\left( {\frac{R_{b}}{R_{0}} - 1} \right)}}$

where P_(E) is the electrical power, T_(avg) is the average temperature across the Pirani gauge, ξ is the temperature coefficient of resistance (1000 ppm/° C. for polysilicon), R_(b) and R₀ are the resistances of the microbridge at a given pressure and ambient pressure, respectively. After the thermal impedance of the Pirani gauge 90 was extracted by a linear curve fit applied to the power vs. temperature data measured at each calibration pressure, the data was plotted as shown in FIG. 15. The long-term hermeticity was monitored by reading the thermal impedance change of the Pirani gauge 90 over time. The thermal impedance changes of two sealed Pirani gauges 90 with different gauge dimensions over one year are shown in FIG. 16. The result shows no noticeable pressure change (<30 mTorr) for a period of time in excess of one year.

To demonstrate the usefulness of this technique for common surface micromachining processes, the Multi-User MEMS Processes, or MUMPS, was selected to fabricate a micro-bridge device 120 encapsulated by the porous polysilicon shell 122. MUMPS is a popular commercial foundry service that provides cost-effective, proof-of-concept MEMS fabrication. One of the standard processes in the MUMPS program is PolyMUMPs, a three-layer polysilicon surface micromachining process, whose thickness data is listed in Table 1 below. TABLE 1 Material layer Thickness (μm) Nitride 0.6 Poly 0 0.5 First Oxide 2.0 Poly 1 2.0 Second Oxide 0.75 Poly 2 1.5 Metal 0.5

FIGS. 17A and 17B schematically represent a fabrication process for integration with MUMPS. Poly1 and Poly1 layers were used to construct the microbridge resonator 120 inside the Poly2 shell 122. Supporting posts 124 were designed to reinforce the polysilicon shell 122 of large size. A sacrificial oxide was used to isolate the polysilicon shell 122 from the electrical feedthrough 126. The post process on the MUMPS chip started in-house with the removal of all the layers on the backside by RIE, a step necessary to create the electrical contact to the Poly2 layer through the substrate for electrochemical etching. Using photoresist as a mask, part of the Poly2 encapsulation layer was turned porous by electrochemical etching. The bridge structure 120 was then released in one minute in concentrated 49% HF, followed by rinsing and supercritical CO₂ drying.

While embodiments of the present invention have been shown and described, various modifications may be made without departing from the scope of the present invention. The invention, therefore, should not be limited, except to the following claims, and their equivalents. 

1. A method of forming a free standing microstructure comprising: providing a substrate; forming a sacrificial layer on the substrate; forming a thin-film structural layer around and over the sacrificial layer; introducing nanometer scale pores in the thin-film structural layer; and etching at least a portion of the sacrificial layer under the thin-film structural layer.
 2. The method of claim 1, further comprising the step of depositing a sealing layer over the porous thin-film structural layer.
 3. The method of claim 1, further comprising the step of forming a one or more microdevices on the substrate in a location disposed beneath the thin-film structural layer.
 4. The method of claim 1, wherein the sacrificial layer is a non-conductive sacrificial layer selected from the group consisting of polymers and ceramics.
 5. The method of claim 1, wherein the thin-film structural layer comprises an encapsulation microstructure that is substantially closed.
 6. The method of claim 1, wherein a seed layer is deposited prior to formation of the structural layer.
 7. The method of claim 6, wherein the seed layer is removed prior to etching at least a portion of the sacrificial layer under the thin-film structural layer.
 8. The method of claim 1, wherein the sacrificial layer and structural layer are formed at a temperature at or below 300° C.
 9. The method of claim 2, wherein the sacrificial layer, structural layer, and sealing layer are formed at a temperature at or below 300° C.
 10. The method of claim 1, wherein the structural layer is a polymer and pores are introduced therein.
 11. The method of claim 10, wherein the pores are introduced by ion irradiation followed by etching.
 12. The method of claim 1, wherein the structural layer is a metal and pores are introduced therein.
 13. The method of claim 12, wherein the metal is aluminum and an anodization etching process transforms the aluminum structural layer into porous alumina.
 14. The method of claim 1, wherein the structural layer comprises a ceramic and pores are introduced therein.
 15. The method of claim 14, wherein the ceramic comprises silicon and anodization etching transforms the silicon structural layer into porous silicon.
 16. The method of claim 15, wherein the sacrificial layer is electrically non-conductive and the structural silicon is doped to be conductive.
 17. A device produced by the method of claim
 1. 18. The method of claim 2, wherein the sealing layer is substantially impermeable to fluids.
 19. The method of claim 1, further comprising the step of cutting the substrate into a plurality of dies.
 20. The method of claim 1, wherein the substrate comprises a silicon wafer. 